Staff Engineer, Signal and Power Integrity

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  • Staff Engineer, Signal and Power Integrity

    Amkor Technology

    2045 East Innovation Circle

    Engineering, Design

    Degrees Required:
    4 Year Degree

    Employment Type:

    Manages Others:


    • Bachelor's degree in Electrical Engineering with at least 5 years of relevant experience;  Master's or Ph.D. in Electrical Engineering and 5+ years' experience is a plus
    • Strong background in the application of Electromagnetics and High Speed Transmission Line principles related to signal and power integrity
    • Proficiency in time and frequency domain modeling and use of 2D and 3D quasi-static and full-wave electromagnetic field solvers such as Cadence/Sigrity, Ansys, or ADS
    • Experience with IC package layout tools such as Cadence APD or SiP
    • Demonstrated and effective verbal/written communication skills
    • Excellent analytical and problem solving skills
    • Great individual contributor and team player
    • Strong interpersonal skills to work professionally with our customers, global design & simulation teams and EDA tool vendors
    • Track record of working successfully in cross-functional development teams across the globe is a plus
    • Familiarity with Outsourced Assembly and Test (OSAT) industry and understanding of substrate manufacturing and assembly processes is preferred

    Amkor Technology in Tempe, AZ is seeking a full-time electrical engineer with a strong technical background and experience in signal and power integrity related to IC package design. The opportunity involves working directly with our customers, design engineers, simulation engineers, business units, R&D and assembly.

    • Work with design engineers to provide design solutions for high-speed and low speed signals, clocks, power delivery signals, and power and ground planes
    • Provide routing guidelines for high-speed, low-speed, power signals, power and ground planes from bumps to balls
    •      Thorough understanding of the SI and PI associated with bump signals/ground patterns and ability to optimize the balls signal/ground placement to improve the performance
    • Provide package layer counts, stack ups, materials, impedance control, test impedance targets, and optimizing net assignments for signals 
    • Perform simulation/optimization to make sure critical signals meet their required specifications
    • Signal integrity analysis of frequency and time domain simulations for high speed signals and low speed signal following specifications
    • Optimize single ended or differential Insertion loss, Return loss, Xtlk, and power sum Xtlk for differential signaling groups and protocols
    • IR_DROP simulation for the power rails from bumps to balls
    • AC frequency sweep simulation to optimize the high RLC traces to the lower by achieving low resistance and inductance traces
    • Power plane resonance to measure the resonances of the package plans
    • PDN frequency domain and transient time domain analyses for PDN
    • Capable of determining component location, count, and specifications required to meet performance requirements
    • Knowledge of high-speed buss design compliance including DDR3, DDDR4, PCIE3, PCIe4, 10KR, 28 GBPS Ethernet PAM2 and 56 GBPS Ethernet PAM4
    • Work as a team with other signal/power integrity engineers and design engineers to develop electrical design guidelines to optimize package designs

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